CSCBFAH=0, CSCBRAH=0, CSCBFAL=0, CSGTRGBR=0, CSCAFBL=0, CSCARBL=0, CSELCA=0, CSCBRAL=0, CSCARBH=0, CCLR=0, CSELCD=0, CSGTRGBF=0, CSELCC=0, CSGTRGAR=0, CSCAFBH=0, CSELCB=0, CSGTRGAF=0
General PWM Timer Clear Source Select Register
| CSGTRGAR | GTETRGA Pin Rising Input Source Counter Clear Enable 0 (0): Counter clear is disable at the rising edge of GTETRGA input 1 (1): Counter clear is enable at the rising edge of GTETRGA input |
| CSGTRGAF | GTETRGA Pin Falling Input Source Counter Clear Enable 0 (0): Counter clear is disable at the falling edge of GTETRGA input 1 (1): Counter clear is enable at the falling edge of GTETRGA input |
| CSGTRGBR | GTETRGB Pin Rising Input Source Counter Clear Enable 0 (0): Counter clear is disable at the rising edge of GTETRGB input 1 (1): Counter clear is enable at the rising edge of GTETRGB input |
| CSGTRGBF | GTETRGB Pin Falling Input Source Counter Clear Enable 0 (0): Counter clear is disable at the falling edge of GTETRGB input 1 (1): Counter clear is enable at the falling edge of GTETRGB input |
| Reserved | These bits are read as 0000. The write value should be 0000. |
| CSCARBL | GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Clear Enable 0 (0): Counter clear is disable at the rising edge of GTIOCA input when GTIOCB input is 0 1 (1): Counter clear is enable at the rising edge of GTIOCA input when GTIOCB input is 0 |
| CSCARBH | GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Clear Enable 0 (0): Counter clear is disable at the rising edge of GTIOCA input when GTIOCB input is 1 1 (1): Counter clear is enable at the rising edge of GTIOCA input when GTIOCB input is 1 |
| CSCAFBL | GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Clear Enable 0 (0): Counter clear is disable at the falling edge of GTIOCA input when GTIOCB input is 0 1 (1): Counter clear is enable at the falling edge of GTIOCA input when GTIOCB input is 0 |
| CSCAFBH | GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Clear Enable 0 (0): Counter clear is disable at the falling edge of GTIOCA input when GTIOCB input is 1 1 (1): Counter clear is enable at the falling edge of GTIOCA input when GTIOCB input is 1 |
| CSCBRAL | GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Clear Enable 0 (0): Counter clear is disable at the rising edge of GTIOCB input when GTIOCA input is 0 1 (1): Counter clear is enable at the rising edge of GTIOCB input when GTIOCA input is 0 |
| CSCBRAH | GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Clear Enable 0 (0): Counter clear is disable at the rising edge of GTIOCB input when GTIOCA input is 1 1 (1): Counter clear is enable at the rising edge of GTIOCB input when GTIOCA input is 1 |
| CSCBFAL | GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Clear Enable 0 (0): Counter clear is disable at the falling edge of GTIOCB input when GTIOCA input is 0 1 (1): Counter clear is enable at the falling edge of GTIOCB input when GTIOCA input is 0 |
| CSCBFAH | GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Clear Enable 0 (0): Counter clear is disable at the falling edge of GTIOCB input when GTIOCA input is 1 1 (1): Counter clear is enable at the falling edge of GTIOCB input when GTIOCA input is 1 |
| CSELCA | ELC_GPTA Event Source Counter Clear Enable 0 (0): Counter clear is disable at the ELC_GPTA input 1 (1): Counter clear is enable at the ELC_GPTA input |
| CSELCB | ELC_GPTB Event Source Counter Clear Enable 0 (0): Counter clear is disable at the ELC_GPTB input 1 (1): Counter clear is enable at the ELC_GPTB input |
| CSELCC | ELC_GPTC Event Source Counter Clear Enable 0 (0): Counter clear is disable at the ELC_GPTC input 1 (1): Counter clear is enable at the ELC_GPTC input |
| CSELCD | ELC_GPTD Event Source Counter Clear Enable 0 (0): Counter clear is disable at the ELC_GPTD input 1 (1): Counter clear is enable at the ELC_GPTD input |
| Reserved | These bits are read as 00000000000. The write value should be 00000000000. |
| CCLR | Software Source Counter Clear Enable 0 (0): Counter clear is disable by the GTCLR register 1 (1): Counter clear is enable by the GTCLR register |